Dual-edge triggered storage elements and clocking strategy for low-power systems.

Dual-edge triggered storage elements and clocking strategy for low-power systems.

This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the stora...

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Pubblicato in:IEEE Transactions on VLSI systems 13, 5 (2005).
Autore principale: Nedovic, N.
Natura: Articolo
Lingua:English
Soggetti:
Clock distribution network.
Clock frequency.
Clocking strategy.
Design guidelines.
Detailed timing characterization.
Dual-edge triggered flip-flops.
Dual-edge triggered storage elements.
High-performance application.
Low-power systems.
Power characterization.
Power savings.
Timing penalty.