Combined circuit and architectural level variable supply-voltage scaling for low power.

Combined circuit and architectural level variable supply-voltage scaling for low power.

Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to reduce energy by lowering the operating voltage and the clock frequency of processor simultaneously. We propose a variab...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 13, 5 (2005).
第一著者: Hai Li
フォーマット: 論文
言語:English
主題:
L2 miss.
RAM structures.
SPEC2K benchmarks.
Circuit-level complexity.
Clock frequency.
Deterministic clock gating.
Energy overhead.
Energy-efficient processor.
Independent computations.
Latency-hiding techniques.
Low power design.
Operating voltage.
Out-of-order-issue processor.
Performance degradation.
Power dissipation.
Software prefetching.
State machines.
Superscalar pipeline.
Variable supply-voltage scaling.