Schedule-aware performance estimation of communication architecture for efficient design space exploration.
In this paper, we are concerned about performance estimation of bus-based communication architectures assuming that task partitioning and scheduling on processing elements are already determined. Since communication overhead is dynamic and unpredictable due to bus contention, a simulation-based appr...
| Pubblicato in: | IEEE Transactions on VLSI systems 13, 5 (2005). |
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| Autore principale: | |
| Natura: | Articolo |
| Lingua: | English |
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