Layout conscious approach and bus architecture synthesis for hardware

Layout conscious approach and bus architecture synthesis for hardware

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such a...

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Détails bibliographiques
Publié dans:IEEE Transactions on VLSI systems 13, 5 (2005).
Auteur principal: Thepayasuwan, N.
Format: Article
Langue:English
Sujets:
IP core placement.
IP core routing.
JPEG SoC.
Bus architecture synthesis.
Bus complexity.
Bus length.
Hardware/software codesign.
Hierarchical cluster growth algorithm.
Interconnect parasitic.
Latency optimization.
Layout conscious approach.
Network processor.
Select-eliminated method.
Special table structure.
Speed constraints.
Speed optimization.
System optimization.
Systems on chip optimization.
Task communication speed.