Layout conscious approach and bus architecture synthesis for hardware - Thepayasuwan, N.
This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.
Keywords: IP core placement; IP core routing; JPEG SoC; Bus architecture synthesis; Bus complexity; Bus length; Hardware/software codesign; Hierarchical cluster growth algorithm; Interconnect parasitic; Latency optimization; Layout conscious approach; Network processor; Select-eliminated method; Special table structure; Speed constraints; Speed optimization; System optimization; Systems on chip optimization; Task communication speed