APA (7th ed.) Citation

Thepayasuwan, N. Layout conscious approach and bus architecture synthesis for hardware. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Thepayasuwan, N. "Layout Conscious Approach and Bus Architecture Synthesis for Hardware." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Thepayasuwan, N. "Layout Conscious Approach and Bus Architecture Synthesis for Hardware." IEEE Transactions on VLSI Systems, .

Warning: These citations may not always be 100% accurate.