Design-for-testability and fault-tolerant techniques for FFT processors.

Design-for-testability and fault-tolerant techniques for FFT processors.

In this paper, we first propose a novel design-for-testability approach based on M-testability conditions for module-level systolic fast Fourier transform (FFT) arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this t...

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Publicat a:IEEE Transactions on VLSI systems 13, 6 (2005).
Autor principal: Shyue-Kung Lu
Format: Article
Idioma:English
Matèries:
FFT processors.
M-testability conditions.
Butterfly network.
Design for testability.
Design for yield.
Fast Fourier transform arrays.
Fault testability.
Fault-tolerant techniques.
Logic testing.
Multiply-subtract-add module.
Reconfiguration schemes.
Systolic arrays.
Test patterns.