A review of 0.18-μm full adder performances for tree structured arithmetic circuits.

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation ci...

詳細記述

書誌詳細
出版年:	IEEE Transactions on VLSI systems 13, 6 (2005).
第一著者:	Chip-Hong Chang
フォーマット:	論文
言語:	English
主題:	0.18 micron. CMOS digital integrated circuits. CMOS logic styles. CMOS process technology. XNOR outputs. XOR outputs. Area performance. Balanced outputs. Cascaded simulation structure. Digital arithmetic. Full adder performances. Full swing logic. Hybrid logic styles. Hybrid style full adder circuit. Logic devices. Low-voltage full adder cells. Pass logic circuit. Power-delay performance. Stand alone operation. Sum and carry generation circuits. Survival cells. Switching delay problem. Tree structured arithmetic circuits.