Cita APA (7th ed.)

Chattopadhyay, A. GALDS: A complete framework for designing multiclock ASICs and SoCs. IEEE Transactions on VLSI systems.

Cita Chicago (17th ed.)

Chattopadhyay, A. "GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs." IEEE Transactions on VLSI Systems .

Cita MLA (9th ed.)

Chattopadhyay, A. "GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs." IEEE Transactions on VLSI Systems, .