Chattopadhyay, A. GALDS: A complete framework for designing multiclock ASICs and SoCs. IEEE Transactions on VLSI systems.
Chicago-viite (17. p.)Chattopadhyay, A. "GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs." IEEE Transactions on VLSI Systems .
MLA-viite (9. p.)Chattopadhyay, A. "GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs." IEEE Transactions on VLSI Systems, .
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