Zhang, X. High-Speed Architectures for Parallel Long BCH Encoders. IEEE Transactions on VLSI systems.
芝加哥风格引文Zhang, X. "High-Speed Architectures for Parallel Long BCH Encoders." IEEE Transactions on VLSI Systems .
MLA引文Zhang, X. "High-Speed Architectures for Parallel Long BCH Encoders." IEEE Transactions on VLSI Systems, .
警告：这些引文格式不一定是100％准确.