APA引文

Zhang, X. High-Speed Architectures for Parallel Long BCH Encoders. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Zhang, X. "High-Speed Architectures for Parallel Long BCH Encoders." IEEE Transactions on VLSI Systems .

MLA引文

Zhang, X. "High-Speed Architectures for Parallel Long BCH Encoders." IEEE Transactions on VLSI Systems, .

警告:這些引文格式不一定是100%准確.