Zhang, X. High-Speed Architectures for Parallel Long BCH Encoders. IEEE Transactions on VLSI systems.
Cita Chicago (17th ed.)Zhang, X. "High-Speed Architectures for Parallel Long BCH Encoders." IEEE Transactions on VLSI Systems .
Cita MLA (9th ed.)Zhang, X. "High-Speed Architectures for Parallel Long BCH Encoders." IEEE Transactions on VLSI Systems, .
Atenció: Aquestes cites poden no estar 100% correctes.