A Case Study Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.

A Case Study Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.

Current high-end microprocessor designs focus on increasing instruction parallelism and clock frequency at the expense of power dissipation. This paper presents a case study of a different direction, a chip multiprocessor (CMP) with a smaller processor core than a baseline high-end 130-nm 64-bit SPA...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 7 (2005).
Main Author: Ando, H.
Format: Article
Language:English
Subjects:
Chip multiprocessor.
Dense custom macros.
Logical resource reduction.
Performance improvement.
Power improvement.
Transaction processing.