Efficient reconfigurable techniques for VLSI arrays with 6-port switches.
This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large scale integration/wafer scale integration (VLSI/WSI) array under the row and column routing constraints, which has been shown to be NP-complete. The proposed VLSI/WSI array consists of identical proces...
Wydane w: | IEEE Transactions on VLSI systems 13, 8 (2005). |
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1. autor: | |
Format: | Artykuł |
Język: | English |
Hasła przedmiotowe: |