Efficient reconfigurable techniques for VLSI arrays with 6-port switches.

Efficient reconfigurable techniques for VLSI arrays with 6-port switches.

This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large scale integration/wafer scale integration (VLSI/WSI) array under the row and column routing constraints, which has been shown to be NP-complete. The proposed VLSI/WSI array consists of identical proces...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 13, 8 (2005).
Päätekijä: Wu Jigang
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
4-port switch.
6-port switch.
NP-complete.
VLSI routing.
VLSI structure.
VLSI/WSI array.
Compensation approach.
Fault processing element.
Fault-tolerance.
Greedy rerouting algorithm.
Identical processing element.
Very large scale integration.
Wafer scale integration.