BDD decomposition for delay oriented pass transistor logic synthesis.

BDD decomposition for delay oriented pass transistor logic synthesis.

We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipa...

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מידע ביבליוגרפי
הוצא לאור ב:IEEE Transactions on VLSI systems 13, 8 (2005).
מחבר ראשי: Shelar, R.S
פורמט: Article
שפה:English
נושאים:
BDD decomposition.
ISCAS 85 benchmarks.
NAND intensive circuit.
PTL.
XOR intensive circuit.
Arithmetic logic unit.
Binary decision diagram.
Control circuits.
Functional decomposition.
Logic synthesis.
Max-flow min-cut technique.
Network flow graph.
Pass transistor logic.
Static CMOS.