APA (7th ed.) Citation

Shelar, R. BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Shelar, R.S. "BDD Decomposition for Delay Oriented Pass Transistor Logic Synthesis." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Shelar, R.S. "BDD Decomposition for Delay Oriented Pass Transistor Logic Synthesis." IEEE Transactions on VLSI Systems, .