TY  - JOUR
T1  - A hardware Gaussian noise generator using the Wallace method.
JF  - IEEE Transactions on VLSI systems
A1  - Dong-U Lee
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609599337
AB  - We describe a hardware Gaussian noise generator based on the Wallace method used for a hardware simulation system. Our noise generator accurately models a true Gaussian probability density function even at high σ values. We evaluate its properties using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test and 2) an application for decoding of low-density parity-check (LDPC) codes. Our design is implemented on a Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) at 155 MHz; it takes up 3% of the device and produces 155 million samples per second, which is three times faster than a 2.6-GHz Pentium-IV PC. Another implementation on a Xilinx Spartan-III XC3S200E-5 FPGA at 106 MHz is two times faster than the software version. Further improvement in performance can be obtained by concurrent execution: 20 parallel instances of the noise generator on an XC2V4000-6 FPGA at 115 MHz can run 51 times faster than software on a 2.6-GHz Pentium-IV PC.
KW  - Anderson-Darling test.
KW  - FPGA.
KW  - Gaussian noise generator.
KW  - Gaussian probability density function.
KW  - LDPC code.
KW  - Monte Carlo method.
KW  - Wallace method.
KW  - Xilinx Spartan-III XC3S200E-5.
KW  - Xilinx Virtex-II XC2V4000-6.
KW  - Channel coding.
KW  - Chi-square test.
KW  - Communication channels.
KW  - Field-programmable gate array.
KW  - Hardware simulation system.
KW  - Low-density parity-check code.
KW  - Reconfigurable-computing.
KW  - Statistical test.
KW  - Technology-mapping.
ER  -