Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).

In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock perio...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:	IEEE Transactions on VLSI systems 13, 8 (2005).
Päätekijä:	Joshi, A.J
Aineistotyyppi:	Artikkeli
Kieli:	English
Aiheet:	GSI. HSPICE circuit simulation. MINDS. SLIP technique. TDM. VLSI system. WPM routing. WPM wire circuits. Circuit level verification. Digital design. Gigascale integration. Interconnect routing. Intraclock period interconnect. Multilevel interconnect network design simulator. On-chip wiring. System level analysis. System level interconnect prediction. Time-division multiplexing. Wave pipelining. Wave-pipelined multiplexing. Wire sharing.