Design of a low power wide-band high resolution programmable frequency divider.

The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs....

पूर्ण विवरण

ग्रंथसूची विवरण

में प्रकाशित:	IEEE Transactions on VLSI systems 13, 9 (2005).
मुख्य लेखक:	Yu, X.P
स्वरूप:	लेख
भाषा:	English
विषय:	0.18 micron. 1.8 V. 5 to 6 GHz. 5.8 mW. CMOS digital integrated circuits. Flip-flop. Frequency synthesizers. High speed frequency divider. Phase locked loops. Power consumption. Programmable counter. Programmable frequency divider. Propagation delay. Wireless LAN.