Switch-factor based loop RLC modeling for efficient timing analysis.

Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem ba...

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書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 9 (2005).
第一著者:	Yu Cao
フォーマット:	論文
言語:	English
主題:	Miller factor. RLC netlists. Capacitive coupling. Data-bus wire planning. Distributed RLC lines. High frequency clock design. Inductive coupling. Loop RLC modeling. Neighboring switching patterns. Parasitic extraction tools. Static timing analysis. Switch factor. Timing optimization. Timing uncertainty.