Yu Cao. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Transactions on VLSI systems.
Цитирование в стиле Чикаго (17-е изд.)Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems .
Цитирование MLA (9-е изд.)Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems, .
Предупреждение: эти цитированмия не могут быть всегда правильны на 100%.