APA (7e ed.) Bronvermelding

Yu Cao. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Transactions on VLSI systems.

Chicago (17e ed.) Bronvermelding

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems .

MLA (9e ed.) Bronvermelding

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems, .

Let op: Deze citaties zijn niet altijd 100% accuraat.