Citazione Stile APA (7a Edizione)

Yu Cao. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Transactions on VLSI systems.

Citazione stile Chigago Style (17a edizione)

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems .

Citatione MLA (9a ed.)

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems, .