Cita APA (7a ed.)

Yu Cao. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Transactions on VLSI systems.

Cita Chicago Style (17a ed.)

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems .

Cita MLA (9a ed.)

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems, .