Yu Cao. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Transactions on VLSI systems.
Chicago-Zitierstil (17. Ausg.)Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems .
MLA-Zitierstil (9. Ausg.)Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems, .
Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.