APA (7 ম সংস্করণ) উদ্ধৃতি

Yu Cao. Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Transactions on VLSI systems.

শিকাগো স্টাইল (17 তম সংস্করণ) উদ্ধৃতি

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems .

M.L.A (9 ম সংস্করণ) উদ্ধৃতি

Yu Cao. "Switch-factor Based Loop RLC Modeling for Efficient Timing Analysis." IEEE Transactions on VLSI Systems, .