Customizable elliptic curve cryptosystems.

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2m), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial m...

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Bibliographic Details
Published in:	IEEE Transactions on VLSI systems 13, 9 (2005).
Main Author:	Cheung, R.C.C
Format:	Article
Language:	English
Subjects:	2.6 GHz. 35 MHz. Xeon computer. Xilinx XC2V6000 FPGA. Customised ECC hardware design. Design generator. Elliptic curve cryptosystems. Field multiplier design. Field programmable gate arrays. Hardware designs. Parallel architecture. Parametric model. Public key cryptography. Security. Such serial multipliers. User-defined requirements.