Soft errors issues in low-power caches.

Soft errors issues in low-power caches.

As technology scales, reducing leakage power and improving reliability of data stored in memory cells is both important and challenging. While lower threshold voltages increase leakage, lower supply voltages and smaller nodal capacitances reduce energy consumption but increase soft errors rates. In...

Ausführliche Beschreibung

Bibliographische Detailangaben
Veröffentlicht in:IEEE Transactions on VLSI systems 13, 10 (2005).
1. Verfasser: Degalahal, V.
Format: Artikel
Sprache:English
Schlagworte:
Architectural-level leakage reduction.
Cache decay.
Cache memory reliability.
Circuit level techniques.
Data storage reliability.
Leakage energy consumption.
Leakage optimization.
Leakage power reduction.
Low-power cache design.
Soft error rates.
Voltage scaling.