Compiler-guided leakage optimization for banked scratch-pad memories.

Compiler-guided leakage optimization for banked scratch-pad memories.

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided...

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Vydáno v:IEEE Transactions on VLSI systems 13, 10 (2005).
Hlavní autor: Kandemir, M.
Médium: Článek
Jazyk:English
Témata:
SPM bank idleness.
Banked scratch-pad memories.
Compiler-based leakage energy optimization.
Compiler-guided memory-data layout optimization.
Data migration.
Low-leakage state.
Low-power state.
On-chip scratch-pad memories.