Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.

This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or ar...

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Foilsithe in:IEEE Transactions on VLSI systems 13, 10 (2005).
Príomhchruthaitheoir: Hua Wang
Formáid: Alt
Teanga:English
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