Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.

Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.

This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or ar...

Disgrifiad llawn

Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Transactions on VLSI systems 13, 10 (2005).
Prif Awdur: Hua Wang
Fformat: Erthygl
Iaith:English
Pynciau:
65 nm.
CMOS nanometer technology.
Pareto configurations.
Pareto optimal energy-delay tradeoffs.
Embedded SRAM.
Formalized technique.
Run-time configuration.
Transistor-level implementation.
Variable tapered Pareto buffer design.