Cita APA (7a ed.)

Hua Wang. Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. IEEE Transactions on VLSI systems.

Cita Chicago Style (17a ed.)

Hua Wang. "Variable Tapered Pareto Buffer Design and Implementation Allowing Run-time Configuration for Low-power Embedded SRAMs." IEEE Transactions on VLSI Systems .

Cita MLA (9a ed.)

Hua Wang. "Variable Tapered Pareto Buffer Design and Implementation Allowing Run-time Configuration for Low-power Embedded SRAMs." IEEE Transactions on VLSI Systems, .