APA (7e ed.) Bronvermelding

Hua Wang. Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. IEEE Transactions on VLSI systems.

Chicago (17e ed.) Bronvermelding

Hua Wang. "Variable Tapered Pareto Buffer Design and Implementation Allowing Run-time Configuration for Low-power Embedded SRAMs." IEEE Transactions on VLSI Systems .

MLA (9e ed.) Bronvermelding

Hua Wang. "Variable Tapered Pareto Buffer Design and Implementation Allowing Run-time Configuration for Low-power Embedded SRAMs." IEEE Transactions on VLSI Systems, .

Let op: Deze citaties zijn niet altijd 100% accuraat.