Energy- and time-efficient matrix multiplication on FPGAs.

Energy- and time-efficient matrix multiplication on FPGAs.

We develop new algorithms and architectures for matrix multiplication on configurable devices. These have reduced energy dissipation and latency compared with the state-of-the-art field-programmable gate array (FPGA)-based designs. By profiling well-known designs, we identify "energy hot spots&...

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Publié dans:IEEE Transactions on VLSI systems 13, 11 (2005).
Auteur principal: Ju-Wook Jang
Format: Article
Langue:English
Sujets:
FPGA device.
Configurable hardware.
Energy hot spots.
Energy profiling.
Energy-delay tradeoff.
Energy-efficient matrix multiplication.
Field-programmable gate array.
Linear array.
System-wide energy dissipation.
Time-efficient matrix multiplication.