Cita APA (7th ed.)

Chatterjee, B. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Transactions on VLSI systems.

Cita Chicago (17th ed.)

Chatterjee, B. "Design of a 1.7-GHz Low-power Delay-fault-testable 32-b ALU in 180-nm CMOS Technology." IEEE Transactions on VLSI Systems .

Cita MLA (9th ed.)

Chatterjee, B. "Design of a 1.7-GHz Low-power Delay-fault-testable 32-b ALU in 180-nm CMOS Technology." IEEE Transactions on VLSI Systems, .