APA (7 वां संस्करण) प्रशस्ति पत्र

Chatterjee, B. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Transactions on VLSI systems.

शिकागो शैली (17वां संस्करण) प्रशस्ति पत्र

Chatterjee, B. "Design of a 1.7-GHz Low-power Delay-fault-testable 32-b ALU in 180-nm CMOS Technology." IEEE Transactions on VLSI Systems .

एमएलए (9वां संस्करण) प्रशस्ति पत्र

Chatterjee, B. "Design of a 1.7-GHz Low-power Delay-fault-testable 32-b ALU in 180-nm CMOS Technology." IEEE Transactions on VLSI Systems, .