Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.

With increasing inter-die and intra-die parameter variations in sub-100-nm process technologies, new failure mechanisms are emerging in CMOS circuits. These failures lead to reduction in reliability of circuits, especially the area-constrained SRAM cells. In this paper, we have analyzed the emerging...

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Foilsithe in:IEEE Transactions on VLSI systems 13, 11 (2005).
Príomhchruthaitheoir: Qikai Chen
Formáid: Alt
Teanga:English
Ábhair:
CMOS circuits.
March test sequences.
SRAM cache.
SRAM cells.
SRAM failure mechanisms.
SRAM testing.
Design for testability.
Double sensing technique.
Fault models.
Inter-die parameter variations.
Intra-die parameter variations.
Process variations.