00000cab a22000003a 4500 UP-99796217609599275 Buklod 20231007234434.0 m |o d | ta 110111s xx d | ||r ||||| || DENGII eng Strollo, A.G.M. A novel high-speed sense-amplifier-based flip-flop. pp. 1266-1274 A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-2MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-μm technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications. 0.25 micron. CMOS digital integrated circuits. Clock-to-output delay. Glitch-free operation. High-speed direct digital frequency synthesizer chip. High-speed flip-flop. Sense amplifiers. Set-reset latches. Short-circuit power dissipation reduction. IEEE Transactions on VLSI systems 13, 11 (2005). FO UPD DENG-II Article