Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.
We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and tem...
| Yayımlandı: | IEEE Transactions on VLSI systems 13, 11 (2005). |
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| Materyal Türü: | Makale |
| Dil: | English |
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