Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.

Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building blo...

সম্পূর্ণ বিবরণ