Efthymiou, A. Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Transactions on VLSI systems.
Cita Chicago (17th ed.)Efthymiou, A. "Test Pattern Generation and Partial-scan Methodology for an Asynchronous SoC Interconnect." IEEE Transactions on VLSI Systems .
Cita MLA (9th ed.)Efthymiou, A. "Test Pattern Generation and Partial-scan Methodology for an Asynchronous SoC Interconnect." IEEE Transactions on VLSI Systems, .
Atenció: Aquestes cites poden no estar 100% correctes.