Dyfyniad APA

Efthymiou, A. Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Transactions on VLSI systems.

Dyfyniad Arddull Chicago

Efthymiou, A. "Test Pattern Generation and Partial-scan Methodology for an Asynchronous SoC Interconnect." IEEE Transactions on VLSI Systems .

Dyfyniad MLA

Efthymiou, A. "Test Pattern Generation and Partial-scan Methodology for an Asynchronous SoC Interconnect." IEEE Transactions on VLSI Systems, .

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.