Bus encoding for total power reduction using a leakage-aware buffer configuration.

Bus encoding for total power reduction using a leakage-aware buffer configuration.

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 13, 12 (2005).
第一著者: Rao, R.R
フォーマット: 論文
言語:English
主題:
Buffer circuit design.
Bus encoding.
Capacitive crosstalk.
Encoding logic complexity.
High-threshold voltage transistor.
Leakage-aware buffer configuration.
On-chip buses.
Runtime leakage power.
Total power reduction.