TY  - JOUR
T1  - Wire retiming as fixpoint computation.
JF  - IEEE Transactions on VLSI systems
A1  - Chuan Lin
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609598941
AB  - In system-on-chips (SOCs), a nonnegligible part of operation time is spent on global wires with long delays. Retiming-that is moving flip-flops in a circuit without changing its functionality-can be explored to pipeline long interconnect wires in SOC designs. The problem of retiming over a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be inserted on some wire segments is called the wire retiming problem. In this paper, we formulate the constraints of the wire retiming problem as a fixpoint computation and use an iterative algorithm to solve it. Experimental results show that this approach is multiple orders more efficient than the previous one.
KW  - Circuit modeling.
KW  - Circuit optimization.
KW  - Constraint formulation.
KW  - Fixpoint computation.
KW  - Interconnects.
KW  - Iterative algorithm.
KW  - Problem solving.
KW  - System-on-chip.
KW  - Wire retiming.
ER  -