Multi chip package lot size optimization using linear programming - Alano, Rina U.
Batching scheme for the incoming multi-chip products scheduled for production at Cavite Flash factory this 3rd Quarter of the year is still unknown. Stores are responsible for the batching process of the multi-chip package from distributing to the line. Lot size of the multi chip package must be determine to ensure that excess or scrap units from fabrication lot raw materials and scrap of goods units in a lot must be minimize and the capacity of Assembly and Test is fully utilize. Multi-chip package (MCP) is composed of top and bottom diets. Top package composed of three types of dies namely Chip A, Chip B, and Chip C while bottom package is one die only which is Chip D. Lead lot refers to main die that carry the attribute of the top and bottom package. The lead for top package is Chip B since it is more costly and due to constrained condition on its batching scheme. The lead lot among the four dies stack multi-chip package is Chip D since it has a higher density among the dies and the logic of the whole chip set. Flash Product Group would like to determine optimal lot size that would maximize the profit gain on multi-chip package. Also to determine the excess/scrap units from raw materials if any on the lead lots of top and bottom package from their respective fabrication lot and to determine batching scheme that will maximize the Assembly and Test capacity. manufacturing must meet this goal without violating the production systems rules and regulations. Linear Programming is used to determine the optimal lot size for the top and bottom multi-chip package that would maximize the profit gain in a lot multi-chip package and minimize the scrap units from the fabrication lot or raw materials and scrap good units (dies with no pairs). The technique is appropriate since the model characterized the LP conditions and makes the problem into simplified form. The Microsoft Excel Solver is used to run the mathematical model. The multi chip package lot size model is composed of 8 decision variables and 10 constraints. Three scenarios are run in the Solver and the recommended batching scheme would be merge or combine 4 Test Process Order (TPO) lots at top package to from 1 lot to be processed to Finished Process Order (FPO) which is use in Scenario 1 and Scenario 3. Optimal lot size value of APO stack top package (Chip A + Chip B + Chip C) is 1000 units, APO bottom package (Chip D) is 500 units, TPO stack top and bottom package is 2000 units (at 90% yield this would become 1800 units) with no excess units from supply at APO top package on Chip A, Chip B, Chip C and has a scrap of 425 units on Chip D at APO bottom package from its fabrication lot or raw materials for scenario 1 while zero for Scenario 3. It would be better to merge 4 TPO lots at top package instead of merging of 3 TPO lots at top package because with this batching plan the maximum Finished Process Order (FPO) lot size can be achieved at 2000 units. The capacity at FPO is fully maximize when this batching scheme is use. Maximum expected profit on the multi-chip package is S12750. Scenario 1 and Scenario 3 have same results except that when supply of good die per fabrication (GDPF) is at its minimum there would be no scrap at APO bottom package or from Chip D's fabrication lot or raw materials. Linear Programming indeed help the proponent find better batching scheme for the multi-chip package that would maximize the expected profit on multi-chip package.