Resource allocation in x86 simultaneous multithreading (SMT) processors - Ancajas, Dean Michael Blasco (2010)
This work addresses resource allocation on an x86 Simultaneous Multithreading processor (SMT). SMT processors increase system resource utilization and throughout by exploiting both Thread-Level parallelism and Instruction level parallelism. In SMT processors, multiple threads are running together and share resources at the microarchitectural level. In this work we evaluated the performance impact and resource utilization of different allocation policies employed on the bandwidth and major storage queues in the pipeline (Fetch Queue and ROB). Multiprogram workloads from the SPEC 2000 suite were selected using microarchitecture independent characteristics[13], principal components analysis and k-means cluster analysis[36] to maximize differing characteristics of the programs and reduce simulation time. Full-system evaluation of two-threaded workloads shows that any allocation policy applied to both the front-end (fetch, rename, allocate) and back-end (ROB) resources of the pipeline only achieves modest performance impact on average because of the low ILP of applications. Furthermore, cycle-level analysis of 13 workloads shows that the overall performance of an SMT processor is maximized when there is a balance in the number of floating point and integer instructions executed between two threads. It is also found that L2 cache miss rate is a good indicator of program performance in SMT execution. Specifically, programs with low (<1%) miss rates tend to perform worse than programs with (>10%) rates because the latter provides more opportunity for other threads to be executed whenever there is a memory miss. This is contrary to previous ideas[42] that advise high cache miss rate as hindrance to SMT performance. Finally, this work's results regarding resource utilization suggest that designers of SMT processors can prefer to simplify chip implementations for power and complexity reasons, by equally sharing major storage resources in the pipeline without worrying that they are giving up performance opportunities.
"October 2010"
Thesis (M.S. Electrical Engineering)--University of the Philippines Diliman.
Keywords: Simultaneous multithreading processors