Frequency synthesizers in 90nm CMOS for Wimax receivers - Abaya, Tanya Vanessa Franco
Wireless communications research is gaining more and more interest as demand for high data rates, interoperability and mobility increase. The Worldwide Interoperability for Microwave Access (WiMax) specified in IEEE 802.16 is one popular standard of the many that has been a product of this widespread interest. Another consequence is the increasing significance of studies on on-chip transmitter and receiver physical layers. Thus, evaluation of the performance and component characteristics of different radio frequency devices must be given adequate attention. Moreover, assessment must be done for different integrated circuit fabrication technologies, both in varying scale and material. One such critical device needing evaluation is the local oscillator, implemented using a frequency synthesizer, which must be of faultless condition for correct modulation/demodulation. In 90 nm CMOS, full frequency design and characterization has yet to be investigated and accomplished. In this research, the design of 90nm CMOS frequency synthesizers for a direct conversion fixed Wimax receiver operating at the 5.725 - 5.875 GHz range is given focus. First, four cross-coupled VCO configurations are implemented, each of which are studied in terms of figures of merit such as phase noise and oscillation amplitude. Each are then integrated in a charge-pump phase-locked loop (PLL) circuit to create integer-N frequency synthesizers. The synthesizers are characterized and systematic design flow is developed. Design for the VCOs are on the schematic and layout levels. Meanwhile, the phase/frequency detector and frequency divider circuits are created using Verilog HDL and verified using NCLaunch. Other blocks were designed in schematic view only. A standard 90 nm CMOS pack is used with the aid of tools from Cadence Design System, Inc. Layout design flow also required Mentor Graphics Calibre and Synopsys StarRCXT. Lastly, efficient PLL simulations utilized Matlab and Verilog-A. Results show that 90 nm CMOS 1-volt integer-N PLL synthesizers are generally sufficient as Wimax local oscillators. While a simple cross-coupled NMOS VCO offers the best phase noise response as a free-running oscillator, two tail-biased versions yield comparable performance when integrated in a PLL loop. The three synthesizers that utilize one of three variations of the NMOS VCO were able to achieve less than -67, -85 and -112 dBc/Hz phase noise at 10, 100 and 1000 kHz offsets, respectively. The fourth synthesizer on the other hand, uses a complementary VCO and provides phase noise at 100 kHz offset that is ~ 2 dB short of the WiMax requirement. However, all synthesizers were able to perform well considering parameters such as lock time, spur suppression and power. Each lock time achieved is nearly 50 μs, while the nearest reference and harmonic spur is at least -72 and -20 dBc, respectively. The four frequency synthesizers operate with less than 26mW of power, more than 80% of which is consumed by the VCO.