00000cab a22000003a 4500 UP-99796217609548118 Buklod 20231007234400.0 m |o d | ta 101117s xx d | ||r ||||| || DENGII eng Castro-Pareja, C.R. FAIR a hardware architecture for real-time 3-D image registration. vol. 7, no. 4 pp. 426-434 Mutual information-based image registration, shown to be effective in registering a range of medical images, is a computationally expensive process, with a typical execution time on the order of minutes on a modern single-processor computer. Accelerated execution of this process promises to enhance efficiency and therefore promote routine use of image registration clinically. This paper presents details of a hardware architecture for real-time three-dimensional (3-D) image registration. Real-time performance can be achieved by setting up a network of processing units, each with three independent memory buses: one each for the two image memories and one for the mutual histogram memory. Memory access parallelization and pipelining, by design, allow each processing unit to be 25 times faster than a processor with the same bus speed, when calculating mutual information using partial volume interpolation. Our architecture provides superior per-processor performance at a lower cost compared to a parallel supercomputer. FAIR hardware architecture. Biomedical image processing. Fast automatic image registration architecture. Floating image. Hardware-accelerated registration. Independent memory buses. Memory access parallelization. Multimodality images. Mutual histogram memory. Mutual information. Network of processing units. Partial volume interpolation. Pipelining. Real-time 3-D image registration. Voxel similarity. IEEE Transactions on information technology in biomedicine 7, 4 (2003). FO UPD DENG-II Article