Development of high-current 4H-SiC ACCUFET. - Singh, R.
Planar 4H-SiC accumulation channel field effect transistor (ACCUFET) have been designed, fabricated, and characterized. Detailed design and processing experiments were conducted on relatively large area ACCUFETs to boost their power ratings. A detailed two-dimensional (2-D) design simulation suggests that the optimum spacing between two adjacent p+ regions is approximately 4 μm. A novel process with epitaxial regrowth over ion implanted p+ base region was developed to achieve a high accumulation layer mobility. Process splits from nitrogen-rich post gate oxidation anneals revealed that the lowest on-resistance and optimum threshold voltage were obtained from N2O annealed samples. 550 V blocking voltage with 22 mΩ-cm2 were demonstrated on 2 A 4H-SiC ACCUFETs. Using a newly developed hex-gate design, larger, 20 A 4H-SiC ACCUFETs are presented here with stable high temperature characteristics. In these high-current devices, the threshold voltage decreases linearly from 1.5 V to 0.9 V, while the extracted channel mobility increases from 18 cm2/V-s to 33.6 cm2/V-s as the operating temperature is increased from 30°C to 200°C.
Keywords: 0.9 to 1.5 V; 2 A; 20 A; 2D design simulation; 30 to 200 C; 4 micron; 550 V; MOSFET power switch; N-rich post gate oxidation anneals; SiC; Design optimization; Epitaxial regrowth; Hex-gate design; High accumulation layer mobility; High-current 4H-SiC ACCUFET; High-current devices; On-resistance.; Optimum spacing; Optimum threshold voltage; Oxide processing; Planar accumulation channel FET; Power MOS-based devices; Power ratings; Stable high temperature characteristics; N2O.; N2O annealed samples; Adjacent p+ regions; Ion implanted p+ base region