Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance.

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance.

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reas...

Disgrifiad llawn

Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Transactions on electron devices 50, 2 (2003).
Prif Awdur: Yang-Yu Fan
Fformat: Erthygl
Iaith:English
Pynciau:
Franz 2-band dispersion model.
NMOSFETs.
SiON.
Dielectric constant.
Gate capacitance.
Gate current performance.
High-K gate dielectric stack.
Interfacial layers.
Leakage current.
Low-EOT regime.
Low-gate current regime.
Stacked gate dielectrics modeling.
Transition regions.
HfO2.
Si3N4-SiO2.
ZrO2.