00000cab a22000003a 4500 UP-99796217609500787 Buklod 20231007234452.0 m |o d | ta 101014s xx d | ||r ||||| || DENGII eng Yang-Yu Fan Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance. pp. 433-439 Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si3N4/SiO2, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement. Franz 2-band dispersion model. NMOSFETs. SiON. Dielectric constant. Gate capacitance. Gate current performance. High-K gate dielectric stack. Interfacial layers. Leakage current. Low-EOT regime. Low-gate current regime. Stacked gate dielectrics modeling. Transition regions. HfO2. Si3N4-SiO2. ZrO2. IEEE Transactions on electron devices 50, 2 (2003). FO UPD DENG-II Article